1. Field of the Invention
The present invention relates to the field of reference buffers. More particularly, the present invention relates to a low power reference buffer including an amplifier with very large transconductance and high frequency non-dominant poles and a triple bonding configuration to a large off-chip capacitor that avoids problems related to the lead wire inductance.
2. Description of the Related Art
Many of the newer analog-to-digital (A/D) converters and other switched capacitor integrated circuits (ICs) have a reference buffer integrated on the chip. This approach increases the chip's functionality, reducing the external component count and the overall system cost.
FIG. 1 illustrates a conventional reference buffer. As shown, a reference buffer A.sub.1 is connected between the reference input V.sub.in and the internal reference line 101. Capacitors C.sub.1 and C.sub.2 are parasitic capacitance and switching capacitance on that internal reference line 101, respectively. More specifically, the switching capacitance C.sub.2 is coupled to the internal reference line 201 by a switch S which is, in turn, controlled by a clock CLK. For conventional high speed, high resolution A/D converter designs, capacitances C.sub.1 and C.sub.2 are on the order of 10 picoFarads (pF) with a switching speed at approximately 40 MHz. Moreover, the settling time within 0.01% (for a 12-bit A/D converter) when the MOS switch S closes is less than 1/2 clock cycle or about 12 nanoseconds (ns) or less.
Modeling the reference buffer response with a single dominant pole (exponential settling), the required transconductance gm of the reference buffer is determined by the following expression. ##EQU1##
where T.sub.s =12 ns is the maximum settling time; (C.sub.1 +C.sub.2)=20 pF is the total load capacitance; and n is the number of time constant periods for settling, which, in this case, is 10.
In the above numerical example, the required transconductance gm is in excess of 100 mA/V. It should be noted that Equation (1) does not take into account nonlinear effects for settling (slewing) and the loading of the reference line by the output capacitance of the reference buffer itself.
For high speed circuits, the design requirements of the reference buffer are often achieved with a considerable amount of power dissipation. In practice, a reference buffer cannot be designed in a Complementary Metal-Oxide Semiconductor (CMOS) technology with a power budget below 200-300 mW, which is comparable with the rest of the power dissipation in the analog section of the A/D converter.
Some power savings can be achieved in a bipolar, or BiCMOS technology, because of the inherently larger bipolar transconductance for a given bias current. Even with this more expensive technology, however, power dissipation in the reference buffer remains a significant fraction of the overall power consumption.